Package for high frequency circuits

ABSTRACT

The present invention relates to integrated circuit packaging and methods of manufacturing these. In particular, but not exclusively the present invention relates to improvements in the suppression of spurious wave modes within cavity packages in which are mounted circuits operating at high frequencies, for example Monolithic Microwave Integrated Circuits (MMIC&#39;s).

The present invention relates to integrated circuit packaging andmethods thereof. In particular, but not exclusively the presentinvention relates to improvements in the suppression of spurious wavemodes within cavity packages in which are mounted circuits operating athigh frequencies, for example Monolithic Microwave Integrated Circuits(MMIC's).

BACKGROUND TO THE INVENTION

Radio communication systems, radar systems and image recognition systemsare well known. Examples of such radio communication systems arebroadband radio communication systems that transmit high data rates toand from customer premises, or that are utilized to connect atransmitter to a single or to multiple receivers. Examples of such radarsystems include those used in military or civilian applications for thetracking of distant objects, such as aircraft or vessels, or those usedwithin automobiles for tracking other vehicles on a highway to ensurethat a safe distance is maintained at all times. Examples of suchimaging systems include those used for screening vehicles or persons asan integral part of Homeland security initiatives.

The majority of the above examples operate with frequencies that are inthe range of from 10 to 100 or 200 GHz, and utilize MMIC's comprisingmultiple circuit elements constructed on a single substrate. In manycases the MMIC is accompanied by additional discrete circuit elementsthat improve the performance of the overall system. Examples of suchsystems include multiple stage amplifiers used to amplify low levelsignals, for example a passive imager. Other examples of high frequencypackaged systems include combined transmit/receive subsystems within asingle cavity package, used for example in a radar system where a oneneeds to transmit and receive signals at similar frequencies.

As a result of the limited signal levels and the operating wavelengthsassociated with the above systems, there is a requirement to providesignificant gains within the associated receiving system. These highgains are traditionally achieved using cascaded low noise amplifiers andfilter chains which result in the associated circuit elements beingsensitive to interference from parasitic noise that may be presentwithin (or external to) the package. In addition, to operate at the highfrequencies required, it is necessary to maintain relatively smalldistances between critical components integrated onto a single (or alimited number) of MMIC's contained in a single package. Such high gainsand small distances place constraints on the design and the method ofmanufacturing the receiving elements of the above systems. Unwantedeffects due to spurious radio frequency energy may couple into theMMIC's and be subject to positive feedback where energy is coupled fromone section of the MMIC to another causing either a degradation inperformance, or at the extreme, total failure of the system. Thus caremust be taken both when designing the MMIC's and when placing themwithin the high frequency package to ensure that any spurious radiofrequency energy present within the package is kept to a minimum.

European patent application EP1719175 (Powell) discloses the possibleexistence of resonant spurious energy in the form of standing wavespresent within a cavity package. This application discloses that themode and resonant frequency of the spurious wave are determined by thedimensions of the package which encloses the circuit. Specifically onecan obtain multiple standing waves within a given package depending onthe dimensions. In cases where the resonant frequency associated withthe standing waves lies within the operating bandwidth of the MMIC'scontained within the package, there is a possibility of radiated energycoupling into sensitive parts of the circuitry causing degradation inits performance. One can also experience energy coupling from one partof a circuit to another via such standing waves. There also exists adanger of oscillation occurring in the case of coupling from the outputof an amplifier to the input of the amplifier, or the input of otherearlier stages of a number of cascaded amplifiers, or into criticalpassive elements associated with the amplifier.

Traditional methods of overcoming the problem of spurious oscillationsinclude, for example, reducing the gain of each stage of the MMICamplifier chain. Such a remedy has the unwanted effect of reducing theoverall performance of the circuit. An alternative method of reducingthe coupling spurious radio frequency energy is to introduce dampingmaterial such as foam into the cavity formed by the package. Anothermethod of reducing the coupling of energy between, for example, atransmitter section to a receiver section of a complex MMIC is to use alow resistance shield which is connected via a low impedance path to thesystem ground.

Several methods and apparatus for reducing the feedback due to couplingof unwanted energy that may take place within the cavity of the packagehave been described in the art. For example international patentapplication number WO92/11665 titled ‘Three-dimensional microwavecircuit carrier and integrated waveguide coupler’, Leicht et al.describes a method for shielding one MMIC from another using conductivescreen(s) molded into the plastic lid of a non-hermetic package. Theconductive screens are connected to earth via receiving posts on theMMIC substrate and may be attached with a conductive epoxy. Thedisadvantages of such a method are that it is limited to applicationswhere there are multiple MMIC's comprising the gain stages of a receiverand the lid cannot be removed without damaging the MMIC. Moreimportantly, such assemblies must be specifically designed for one/eachapplication. This method also increases the spacing between theamplifiers comprising the system, thus limiting the maximum frequency atwhich the system can operate. The operation requires good ground contactbeing made between the underlying substrate and the conductive screens.In practice such a good ground contact may not be readily achieved dueto manufacturing tolerances and/or parasitic inductance associated withthe receiving posts on the MMIC substrate.

Another method is described by Uematsu Hiroshi et al in EP0798782 titled‘Packaging for Microwave Circuits’. This application relates to the useof a dielectric spacer mounted directly on the module carrier on whichthe MMIC circuits are positioned. The dielectric spacer is intended toprevent the occurrence of coupling of unwanted RF between one MMIC andanother. However it would be apparent to one skilled in the art that thedielectric spacers do not limit the occurrence of spurious wave modewithin a cavity package. The use of dielectric within a cavity packagealso has the effect of making the package electrically larger, thuslowering the resonant frequencies associated with the package which mayas a result be modified to an extent that they lie within the operatingbandwidth of the active circuit. Another disadvantage of such a methodis that it is limited to applications where there are multiple MMIC'scomprising the gain stages of a receiver. The use of spacers alsoincreases the distance between the MMIC, thus limiting the maximumfrequency of operation.

Within the patent U.S. Pat. No. 5,416,668, Benzoni describes a novelmethod of constructing a well grounded shield between two distinctcircuit elements comprising a high frequency transmitting/receivingsystem. The system utilizes a conductive shield, constructed as part ofthe lid of the package. The shield is earthed to the side walls of thecavity of the package utilizing integral mounting posts when the twosection pieces of the package are assembled together. Thus the shieldeffectively prevents leakage of radio frequency energy from one subcavity to another. However, the method fails to prevent or reduce theformation of parasitic standing waves within sub cavities formed by theshield, for example as described by Powell. The system also onlyoperates if one can electrically isolate sub-elements of a complexsystem from each other without the shield interfering with the desiredperformance. Thus one can conclude that the ideas presented by Benzoniare limited in their range of applications, do not reduce energyassociated with parasitic standing waves, and the shielding member(s)(and associated package) need to be custom designed for a specificsystem.

U.S. Pat. No. 5,608,188 (Multi Compartment Electromagnetic EnergyShield) in the name of Choon et al. discloses a method of constructing awell grounded shield between two distinct circuit elements comprising ahigh frequency transmitting/receiving system. The system utilizes afloating shielded member to ensure that the base of the shield is inclose contact with an earth stripe that is placed between the twodistinct parts system housed within the package. Thus, in a similarmanner to that described by Benzoni, the shield effectively preventsleakage of radio frequency energy from one sub-cavity to another. Tooperate, the shield described by Benzoni is also dependent on theability of electrically isolate sub element of a complex system one fromthe other without the shield interfering with the desired performance.Thus one can conclude that the ideas presented by Choon et al. arelimited in their range of application, do not reduce energy associatedwith parasitic standing waves, and the shielding member(s) andassociated MMIC again need to be custom designed for a specific system.

Within U.S. Pat. No. 6,862,001 titled ‘High Frequency CommunicationDevice’ Kondoh et al. describe an alternative method for reducing thecoupling of radio frequency energy from one circuit element to anotherutilizing a filter. Within the patent Kondoh et al describe the regularstructure that reduces radio energy at the operating frequency of theenclosed MMIC and not spurious energy that is associated with thepackage itself. The frequency at which the filter operates is defined bythe mark space ratio of the periodic mechanical structure that is builtinto the lid of package, and is specifically designed to coincide withthe frequency of operation of the underlying circuitry. However, thestructure can modify the desired operation of the underlying circuitryif the lower extremity of the periodic structure is in close proximityto the surface of the active circuitry. From the description presentedit is clear that the filter is intended to reduce coupling of energyfrom one part of a circuit to another at the operating frequency of theunderlying circuitry. Thus the periodic structure that forms the filterhas to be specifically designed in conjunction with the MMIC.

US patent application number US20050274932 titled ‘Shielding forElectromagnetic Interference’ by Knight et al., presents an alternativemethod of reducing the energy coupling from one circuit element toanother within a multiple MMIC system. The concept focuses on the use ofa composite liquid crystal polymer loaded with an electricallyconductive material to form a shield that is thermally matched to a lowcost plastic cavity package. Knight et al. describe the action ofdesigning the shielding member such that the lower extremity lies withina fraction of a wavelength of the underlying substrate onto which theactive circuits are mounted. Maintaining such a minimum distance isintended to limit the leakage of radio frequency energy from one subcavity to another at the operating frequency of the enclosed circuitry.Knight et al. further describe the anisotropic nature of the conductivematerial forming the shield which reduces the potential effect of theshield on the desired operation of the circuit elements. Although thestructure described will reduce the coupling of energy (at the operatingfrequency) from one sub cavity to another, the shield and the underlyingcircuits have to be specifically designed in conjunction with each otherto ensure that the shield does not impact the desired operation of thesystem.

As mentioned previously, Powell et al. (EP1719175), discloses theexistence of a ‘spurious wave mode’ within the cavity of a highfrequency package. The spurious wave is attributed to the resonantfrequency of cavity dimensions and the associated materials. Powell etal. further describe a method and apparatus for limiting the amount ofenergy present in such spurious modes utilizing a resistive coatedstructure tuned to the impedance of the wave that one would experienceif the structure were not present.

The use of the resistively coated structure reduces the effect of theinteraction of such ‘spurious wave mode’ with sensitive parts of theenclosed circuitry. Powell et al. define that a number of differentmodes of different frequencies can be experienced within a cavitypackage, all of which are dependent on the dimensions of the cavity anddescribe the use of one or more partially conducting vane(s) protrudinginto the package cavity to reduce the energy associated with such waves.The number, size, orientation(s) of the resistive vanes are arranged tocoincide with the points of maximum energy of the standing waves thatwould be present within the cavity if the vanes were not present. Theresistance of the surface of the vanes is designed to match theimpedance of the ‘spurious wave mode’ if the vanes were not present.Although the number, size, orientation and exact position of the vane(s)are stated to be of importance with regard to the extent to which theenergy associated with a spurious mode wave is reduced, there arelimitations as to the placement of the vanes to ensure that they do notinterfere with the enclosed circuitry. In particular it is important toensure that the dielectric structure onto which the resistive materialis supported does not interfere with the operation of the system byloading sensitive areas of the underlying circuit. As with thedisclosures mentioned above it is essential to design the resistivecoated vanes in conjunction with the design of the enclosed MMIC.

Thus a key disadvantage of the methods and apparatus described by Powellis the accuracy required for placement of the vane(s), specifically toreduce higher order spurious wave modes. In addition, the dielectricstructure supporting the resistive vane can either cause a loadingeffect on the circuitry or can themselves create new spurious wave modeswhich degrade the performance of a system that is operating at very highfrequencies (i.e. >80-100 GHz).

Embodiments of the present invention seek to address one or more of thelimitations of known packaging techniques and the systems outlined aboveand to preferably improve the performance thereof. More particularly, itis the aim of the present invention to provide a universal package forencapsulating high frequency electrical circuitry operating atfrequencies above 10 GHz and which suppresses spurious wave modes withinsaid package.

By use of the term ‘universal’ is meant that the package may be usedwith any high frequency electrical circuit (HFEC) and will function tosuppress spurious wave modes regardless of the circuit that it used. Thepackage or more specifically the damping structures therein act tosuppress spurious wave modes in connection with any HFEC and suchdamping structures are not designed around a particular circuit. Thus,in contrast to the prior art packages, specific adaptations to, or priorknowledge of, the circuit design is not required for the dampingstructures to fulfill their role/function.

SUMMARY OF THE INVENTION

Particular and preferred aspects of the present invention are set out inthe accompanying independent and dependent claims.

In a first aspect of the invention there is provided a package having acavity for high frequency electrical circuits capable of generatingresonant wave modes in a range of orientations within the cavity, thecavity formed within a first material for containment of the electricalcircuit, wherein the package additionally comprises a second materialextending into the cavity and comprising a plurality of discreteconductive regions that are configured to uniformly absorb all resonantwave modes across the range of orientations.

The second material forms at least one elongated member or projectionwhich extends into the cavity, for example from a surface of the cavitysuch as the top which may be in the form of a ‘lid’ or from one or moresides of the package which form the cavity. In particular embodimentsthe second material forms at least one elongated member having or beingof substantially polygonal cross-section. Such an elongated member willhave a plurality of sides, for example, three, four, five, six or more.In some embodiments the sides will be substantially straight incross-section. In other embodiments the sides will be curved or may formor comprise curves in cross-section. In yet other embodiments, the sidesmay comprise both straight and curved sides in cross-section. In otherembodiments the second material forms at least one elongated memberhaving a circular cross-section.

In particular embodiments the at least one elongated member is ofgradually decreasing cross-section towards the apex thereof. Thus, suchan elongated member may have an actual point or apex, for example beingconical in shape or form. Alternatively, such an elongated member may beof gradually decreasing cross-section towards an imaginary or projectedapex, for example, such as a cone or pyramid whose tip has beentruncated by a plane substantially parallel to its base. The elongatedmember(s) may be cylindrical. In certain embodiments, the package maycomprise elongated members having different shapes, sizes, volumesand/or cross-sections.

Preferably the shape of the at least one elongated member is one whichhas a high surface area. More particularly the shape may have a highsurface area and a low or lower volume. It is also possible to increasethe surface area of a shape which has smooth surfaces by introducingirregularities. Surface area may also be maximized by utilizingelongated members having an ‘aerated’ or sponge like appearance. Thus,the terms referring to shapes/forms/number of sides and the like areintended to be broadly descriptive and are not intended to excludeirregular shapes or forms that may be created, for example, for thepurpose of increasing surface area.

In particular embodiments the package comprises a plurality of elongatedmembers in an ordered array. In yet other embodiments the packagecomprises a plurality of elongated members in an unordered array. Instill yet other embodiments the package comprises a plurality ofelongated members some of which may be in an ordered array whilst othersare in an unordered array. In still yet further embodiments the packagecomprises a plurality of elongated members that are randomly positioned.

In some embodiments the plurality of discrete conductive regions arepositioned or formed such that when a circuit is contained within thepackage, such conductive regions will be at one or more oblique anglesto any active circuits contained within the package.

In other embodiments the plurality of discrete conductive regions arepositioned or formed such that when a circuit is contained within thepackage, such conductive regions will be substantially perpendicular toany active circuits contained within the package.

In still yet other embodiments the plurality of discrete conductiveregions are positioned or formed such that when a circuit is containedwithin the package, some conductive regions will be at one or moreoblique angles to any active circuits contained within the packagewhilst other conductive regions will be substantially perpendicular toany active circuits contained within the package

Particularly the second material comprises a material selected from thegroup consisting of glass, plastic, ceramic, cardboard, metal andmetalloid. Yet more particularly the second material comprises amaterial selected from the group consisting of alumina, aluminium,brass, boron, germanium, quartz, silicon and silicon dioxide. When thematerial is a plastic, preferably it is a thermoplastic. Other suitablematerials include aerated polymers or gels.

In particular embodiments, the first and second materials comprise orare formed from the same material or materials. Alternatively, the firstand second materials comprise or are formed from different materials.The first and second materials may be shaped or formed at substantiallythe same time or may be shaped or formed separately. When the first orsecond materials are shaped or formed separately they may be bonded oradhered together, for example, using techniques known in the art such asadhesives, welding or mechanical fixing and the like.

In particular embodiments the second material is formed by wet etchingof silicon dioxide. In other embodiments the second material is formedby moulding, particularly injection moulding.

Preferably the second material forms or comprises at least one irregularsurface. Such an irregular surface may be produced when the secondmaterial is shaped or formed. Alternatively such an irregular surfacemay be produced in a subsequent processing step, for example, bymechanical treatment such as drilling, sanding or abrasion or chemicaltreatment such as acid erosion. Preferably the at least one or pluralityof discrete conductive regions are formed on the at least one irregularsurface. In certain embodiments, the entire surface of the secondmaterial is a coated surface, the coating being or comprising theconductive region or regions.

In particular embodiments the discrete conductive regions are formed byelectroplating of the second material. Suitable resistive materials forforming the conductive region or regions include nickel alloys such asnichrome and the like.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 Shows a typical cavity package in cross section housing a typicalhigh frequency circuit e.g. a MMIC. The package typically contains amounting plate (101) onto which one (or more) Monolithic MicrowaveIntegrated Circuit (MMIC) (102) is mounted using an electricallyconductive material. The mounting plate (101) is connected to theelectrical ground of the system and is surrounded on four sides byconductive material to form a screened cavity (103). Typically themounting plate and the side walls are formed from a single piece ofhighly conductive material. A number of electrical connections (104) aremade to the MMIC via conductors that pass through, and are isolatedfrom, the sides of the cavity. To complete the enclosure a lid ofconducting material (105) is placed onto the cavity and is attached viaa material or a method that provides a good electrical connection.

FIG. 2 a shows a simulated structure for a cavity package.

FIG. 2 b simulates the energy at different frequencies present withinthe simulated structure of FIG. 2 a.

FIG. 3 a is a simulated model of a cavity package into which a singleresistively coated vane is placed according to the methodology of Powellet al.

FIG. 3 b simulates the energy at different frequencies present withinthe cavity package of FIG. 3 a.

FIG. 4 a is a damping structure according to the present invention whichcomprises a number of evenly spaced, resistively coated cylinders. Thedamping structure is shown within a typical cavity package.

FIG. 4 b is a simulation of the energy present at different frequencieswithin the cavity package of FIG. 4 a.

FIG. 5 a exemplifies a further damping structure according to thepresent invention. In this instance the damping structure comprises anumber of evenly spaced, resistively coated inverted cones.

FIG. 5 b is a simulation of the effect on energy at differentfrequencies within a cavity package into which the damping structure ofFIG. 5 a is deployed.

FIG. 6 a exemplifies a further damping structure according to thepresent invention which comprises a number of randomly spaced,resistively coated inverted cones.

FIG. 6 b is a simulation of the effect on energy at differentfrequencies within a cavity package into which the damping structure ofFIG. 6 a is deployed.

FIG. 7 exemplifies, by way of non-limiting example, a number ofgeometric shapes that the elongated members of second material may beformed into.

DETAILED DESCRIPTION OF THE INVENTION

Specific embodiments of the invention will now be described, by way ofexample only, and with reference to the accompanying drawings.

Various methods of manufacturing of high frequency circuits operating atfrequencies in the range of 10 GHz to >100 GHz have been describes inthe literature. As shown in FIG. 1, these high frequency circuits oftencontain a mounting plate or cavity (101) onto which one or moreMonolithic Microwave Integrated Circuits (MMIC's) (102) are mounted. Themounting plate is connected to the electrical ground of the systemsurrounded on four sides by conductive material to form a screenedcavity (103). A number of electrical connections (104) are made to theMMIC via conductors that pass through, and are isolated from, the sidesof the cavity. To complete the enclosure, a lid of conducting material(105) is placed onto the cavity and is attached via a material thatprovides an electrical connection. The package of the present inventionmay incorporate these general features. In addition the lid may alsoform or comprise a hermetic seal to secure against the entry of watervapor and/or foreign bodies in order to maintain the proper functioningand reliability of the circuit(s) contained or enclosed within thepackage.

The possible existence of resonant spurious wave modes within a cavitypackage has previously been described in detail by Powell et al. As maybe seen in FIGS. 2 a and 2 b the mode and resonant frequency of thespurious wave within the cavity are determined by the package dimension.In the simulated example there are two resonant cavity modes M1 at 60GHz and M2 at 90 GHz.

In certain situations, where the resonant frequency (or frequencies) ofthe cavity lies within the operating bandwidth of the MMIC's (or supportcircuits) contained within the package, there is a possibility of energyassociated with the spurious wave modes coupling into sensitive parts ofthe circuit, thus causing a degradation in performance. In the case ofparasitic spurious mode energy coupling to the input stage of a highgain amplifier, there is danger of oscillation occurring. Such anoscillation would cause the operation of the circuit to degrade or fail.

Powell et al. describe in detail the method for utilizing a vane coatedto reduce the energy associated with the spurious wave modes. Theresistance of the partially conductive material is selected to match theimpedance of the spurious wave which would exist if the resistivelycoated vane were not present. Powell et al. further describe theposition of the vane(s) to coincide with the points where maximum energyof the spurious wave modes would be seen to occur.

FIGS. 3 a and 3 b, demonstrate a single vane placed along the centralaxis of the cavity such that it coincides with the points of maximumenergy of the spurious wave mode. As described by Powell et al, thissingle vane has the effect of significantly reducing the energyassociated with the primary spurious wave mode. However, it can clearlybe seen in FIG. 3 b that the low dielectric structure onto which theresistive material is coated has the effect of increasing the effectivedimensions of the cavity and thus reducing the resonant frequency,whilst also reducing the amount of energy present in the spurious wavemode. Furthermore a single vane positioned on the center axis of thepackage will only suppress even order spurious wave modes. Thus to fullysuppress the spurious wave modes one would need to place additionalresistive vanes within the package at locations (and in directions)where the points of maximum energy associated with higher order and bothodd and even order spurious wave modes would exist.

By placing additional resistive vanes within the cavity as defined byPowell et al, one can suppress some modes, but one can also generate newhigher order modes formed by the affect of the damping structure(s) andthe underlying circuitry. For example, a spurious wave can be formed asa result of the formation of transmission paths between the bottom ofthe dielectric vanes (supporting the resistive coating) and theunderlying MMIC. Under some circumstances these higher order modes,which are difficult to suppress, can be present within the operatingbandwidth of the MMIC. For example it can be seen in FIG. 3 b that asingle vane has the effect of introducing a higher order spurious wavemode (M5), the frequency of which may extend into the operatingbandwidth of the underlying circuit.

These new spurious modes are created by fields concentrated between thelow dielectric structure necessary to support the resistive vane and theMMIC. The energy associated with these new higher order modes can bereduced by changing the support structure of the resistive material tothe form of a field of cylinders evenly spaced within the cavity asshown in FIGS. 4 a and 4 b.

Further reduction in higher order spurious wave modes can be achieved byreducing the area of the three-dimensional structures that are in closeproximity to the MMIC. The Inventors have discovered that this may bedone by utilising three-dimensional structures having a graduallydecreasing cross-section towards the apex, formed from a second materialas defined above. For example, by using a number of inverted cones asshown in FIGS. 5 a and 5 b, or alternatively as shown in FIGS. 6 a and 6b.

The use of the inverted cone structure(s) (as defined above) effectivelyreduces the volume of material that is in close proximity to the activeMMIC, thus reducing any loading effect on sensitive parts of thecircuit. Thus with this innovative step one can design a universalsystem for the suppression of spurious wave modes within a cavitypackage, whilst also reducing the energy associated with the loading ofthe damping structure itself on the underlying MMIC. It is evident fromthe simulated performance shown in FIGS. 5 b and 6 b, that with thisinnovation, one can design a universal damping system that can operateat high frequencies independent of the type of MMIC that is housedwithin the package cavity.

In both the case of the resistively coated cylinders and the resistivelycoated inverted cones, the material (second material) selected to formthe shapes can be a low dielectric material such as a semiconductor,rather than a material as disclosed by Powell et al. In addition theresistive material (that forms the conductive regions) used to uniformlyresistively coat the cylinders does not need to be specifically matchedto the impedance of the original spurious wave mode. Thus themanufacturing of the resistively coated cylinders/cones can be realisedusing modern semiconductor processing techniques as further describedbelow.

As described above the material utilised to manufacture thethree-dimensional structures (e.g. a sequence of coated cylinders orinverted cones) can be of a form that is easily manufactured such as asemiconductor material. The advantage of semiconductor material is thatmany techniques have been previously developed to construct multipleinstances of three-dimensional shapes in a single large silicon wafer(i.e. wafer scale manufacturing), which leads to higher reproducibilityand lower manufacturing cost.

Examples of such wafer scale silicon manufacturing techniques that canbe utilised to realise the structures defined above are for example:

Repeated deposition and wet etching of silicon dioxide onto a siliconsubstrate to form a three dimensional shape using techniques thatsimilar to those used for the fabrication of micro machines. The use ofwet etching techniques to manufacture 3D forms has been a standardprocess used within the semiconductor industry for 30-40 years and iswidely reported in the literature. The manufacture of an isolated conefor example, may comprise the following steps:

-   -   1) Grow a thick layer of silicon dioxide onto the surface of a        clean silicon substrate contained within an oxygen rich        environment using a high temperature.    -   2) Spin on an even coating of a photo resistant layer.    -   3) Place in close proximity a photo mask in with a hole of        diameter ‘X’ and illuminate with a light of a frequency that        hardens the area of the photo resist that is in close proximity        to the hole.    -   4) Remove the excess photo resist which is not hardened using a        suitable liquid rinse (e.g. DI water).    -   5) Immerse the silicon substrate into a suitable liquid (e.g.        Hydrofluoric acid) to remove the area of silicon dioxide that        lies outside of the area protected by the hardened photoresist        for a specific duration that is sufficient to remove the maximum        amount of silicon dioxide whilst not undercutting below the        hardened photoresist.    -   6) Rinse the etched silicon substrate in a suitable liquid (e.g.        DI water) to remove excess acid.    -   7) Remove the hardened resist using a suitable liquid or etching        process.    -   8) Repeat the process 1 & 2 above.    -   9) Place a second mask in close proximity to the patterned        silicon wafer which has a hole (concentric with the hole in the        first mask) which has a diameter which is smaller than the first        hole (e.g. a diameter of 80% X).    -   10) Repeat the steps 4 through 8.    -   11) Repeat step 9 with third mask which a hole that is        concentric to that within the first mask with a hole that is        further reduced in size (e.g. 60% X).

From the process above it would be clear to one skilled in the art thatone can build a structure of a specific height and of a specific formthat is dependent on the relative shape of the holes that are containedwithin the photo masks. It is also apparent to one skilled in the artthat one could utilize similar manufacturing techniques to build anarray of structures of similar form.

Once the array of structures or elongated members is formed the arraycan be coated with a material of the required resistance using eitherdeposition or electro plating.

Other methods of manufacture include:

-   -   Injection moulding of a plastic shape onto an underlying        substrate. The plastic used for the injection is loaded with or        comprises microspheres of a conductive material, to enable the        shape to be subsequently electroplated with the resistive        material.    -   The moulding of a shape directly onto a silicon substrate        utilizing epoxy resin loaded with micro spheres of conductive        material for example by way of the REEMO® UV replication        processes (such as in EP1837166 and EP1542074). Once cured the        resulting 3D shapes can be electroplated with the resistive        coating.    -   Further information relating to silicone etching may be found        at: www.virginiasemi.com/pdf/siliconetchingandcleaning.pdf        (herein incorporated by reference and as an Appendix).

Wet-Chemical Etching and Cleaning of Silicon January 2003 VirginiaSemiconductor, Inc. 1501 Powhatan Street, Fredericksburg, Va. 22401(540) 373-2900, FAX (540) 371-0371

www.virginiasemi.com, tech@virginiasemi.com

A INTRODUCTION

Research and manufacturing related to silicon devices, circuits, andsystems often relies on the wet-chemical etching of silicon wafers. Thedissolution of silicon using liquid solutions is needed for deep etchingand micromachining, shaping, and cleaning. Also, wet-chemistries areoften used for defect delineation in single crystal silicon materials.In this paper, a review of the typical wet-chemical recipes used byengineers is given. As many sources as possible have been used topresent a concise listing of etchants and processes.

B WAFER CLEANING

A sequence of chemistries is typically used to clean silicon wafers.This sequence was first developed at the RCA laboratories, and istherefore often referred to as the RCA process. This chemical sequencedoes not attack the silicon material, but selectively removes theorganic and inorganic contamination that resides on the wafer surface.The following is a typical RCA process; many variations to the orderingof the sequence and chemical ratios are used throughout the industry.

-   -   General Clean: A general cleaning is accomplished by using a        mixture of Sulfuric Acid and Hydrogen Peroxide. Mixing these        chemicals is dangerous and generates extreme heat. This industry        standard clean removes organic and inorganic contamination from        the wafer. 2-10 minute clean is recommended. Strong rinse in DI        water is required after this cleaning step.    -   Particle Removal: A Megasonic clean (at about 70 C) in a 5:1:1        ratio mixture of DI water:Ammonium Hydroxide:Hydrogen Peroxide        will remove silica and silicon particles from the wafer, as well        as remove certain organic and metal surface contamination. 2-10        minute clean is recommended. Strong rinse in DI water is        required after this cleaning step.    -   Oxide Removal: A 15-60 second dip in 1:20 HF:DI water will        remove the native oxide layer and any contamination in the oxide        from the wafer surface. HF is extremely dangerous and must be        handled with great care. Strong rinse in DI water is required        after this cleaning step.    -   Metal Contamination Removal: A Megasonic clean (at about 70 C)        in a 6:1:1 ratio mixture of DI water:HCL:Hydrogen Peroxide will        remove certain ionic and metal surface contamination. 2-10        minute clean is recommended. Strong rinse in DI water is        required after this cleaning step.    -   Spin Rinse Dry: Wafers should be rinsed and dried in a standard        spin-rinse dryer.

Megasonic agitation is commonly used with the chemical bath and mostcommonly with the particle removal step. Also, heavy DI rinse steps areused between each chemical treatment. DI rinsing may use dump-baths,over-flow baths, and spray-dump baths, as well as combinations. Properremoval of all cleaning chemistry with 18 MegaOhm DI water is criticaland needed after each chemical bath. Any text book on the topic ofsemiconductor or silicon processing is an excellent resource for furtherinformation regarding the RCA cleaning process (for example see S. Wolfand R. Tauber, “Silicon Processing:Vol. 1”, Lattice Press, CA, 1986).

There are commercially available premixed cleaning solutions that can beused directly to clean wafers and serve the same purpose of the RCAcleaning process. These chemicals typically achieve the function ofseveral cleaning steps with one solution (see for example JT Baker,Baker Clean Solution).

C ANISOTROPIC KOH ETCHING

KOH is one the most commonly used silicon etch chemistry formicromachining silicon wafers.

1. Anisotropic KOH Etching Rates vs. Orientation

-   -   The KOH etch rate is strongly effected by the crystallographic        orientation of the silicon (anisotropic). Table 1 relates        silicon orientation-dependent etch rates (μm min⁻¹) of KOH to        crystal orientation with an etching temperature of 70° C. Table        1 is taken directly from [1]. In parentheses are normalized        values relative to (110).

Crystallographic Rates at different KOH Concentration Orientation 30%40% 50% (100) 0.797 (0.548) 0.599 (0.463) 0.539 (0.619) (110) 1.455(1.000) 1.294 (1.000) 0.870 (1.000) (210) 1.561 (1.072) 1.233 (0.953)0.959 (1.103) (211) 1.319 (0.906) 0.950 (0.734) 0.621 (0.714) (221)0.714 (0.491) 0.544 (0.420) 0.322 (0.371) (310) 1.456 (1.000) 1.088(0.841) 0.757 (0.871) (311) 1.436 (0.987) 1.067 (0.824) 0.746 (0.858)(320) 1.543 (1.060) 1.287 (0.995) 1.013 (1.165) (331) 1.160 (0.797)0.800 (0.619) 0.489 (0.563) (530) 1.556 (1.069) 1.280 (0.989) 1.033(1.188) (540) 1.512 (1.039) 1.287 (0.994) 0.914 (1.051) (111) 0.005(0.004) 0.009 (0.007) 0.009 (0.010)

-   -   The (110) plane is the fastest etching primary surface. The        ideal (110) surface has a more corrugated atomic structure than        the (100) and (111) primary surfaces. The (111) plane is an        extremely slow etching plane that is tightly packed, has a        single dangling-bond per atom, and is overall atomically flat.        As shown above, the strongly stepped and vicinal surfaces to the        primary planes are typically fast etching surfaces.

2. KOH Etching Rates vs. Composition and Temperature

-   -   Table 2 relates silicon orientation-dependent etch rates of KOH        to percent composition, temperature, and orientation. Table 2 is        taken directly from [2]. As with all wet-chemical etching        solutions, the dissolution rate is a strong function of        temperature. Significantly faster etch rates at higher        temperatures are typical, but less ideal etch behavior is also        common with more aggressive etch rates. Also, heavy boron doping        can significantly harden the silicon and sharply reduce the etch        rate.

Etch Tem- rate perature Direction (μm Etchant (° C.) (plane) min⁻¹)Remarks Reference 20% KOH: 20 (100) 0.025 Near Peak [3] 80% H₂O 40 (100)0.188 etch rate at the 60 (100) 0.45 conc. across 80 (100) 1.4temperature 100 (100) 4.1 30% KOH: 20 (100) 0.024 Smoother [3] 70% H₂O40 (100) 0.108 surfaces than 60 (100) 0.41 at lower 80 (100) 1.3concentration 100 (100) 3.8 Faster etch 20 (110) 0.035 rate for (110) 40(110) 0.16 than for (100) 60 (110) 0.62 80 (110) 2.0 100 (110) 5.8 40%KOH: 20 (100) 0.020 [3] 60% H₂O 40 (100) 0.088 60 (100) 0.33 80 (100)1.1 100 (100) 3.1 20% KOH: 20 (100) 0.015 Lower etch [3] 80% 4 40 (100)0.071 rate H₂O: 1 60 (100) 0.28 Smoother IPA) 80 (100) 0.96 Less 100(100) 2.9 undercutting Lower (100): (111) etch-rate ration 44% KOH: 120(100) 5.8 High [4] 56% H₂O (110) 11.7 Temperature (111) 0.02 23.4% 80(100) 1.0 Sensitive to [5] KOH: (110) 0.06 boron 63.3% concentrationH₂O: 13.3% IPA

D ANISOTROPIC TMAH (TETRAMETHYLAMMONIUM HYDROXIDE) ETCHING

Similar to KOH etching, TMAH is commonly used for fast removal andsilicon micromachining

1. TMAH Etching Rates Vs. Orientation

-   -   The orientation dependence of the TMAH etch rate is similar to        KOH and varies similarly in accordance to the atomic        organization of the crystallographic plane. Table 3 relates        silicon orientation-dependent etch rates of TMAH (20.0 wt %,        79.8° C.) to orientation. Table 3 is taken directly from [6].

Etching rate Etching rate ratio Orientation (μm min⁻¹) (i j k)/(100) (ij k)/(111) 100 0.603 1.000 37 110 1.114 1.847 68 210 1.154 1.914 70 2111.132 1.877 69 221 1.142 1.894 69 310 1.184 1.964 72 311 1.223 2.028 74320 1.211 2.008 73 331 1.099 1.823 67 530 1.097 1.819 66 540 1.135 1.88269 111 0.017 0.027 1

2. TMAH Etching Rates vs. Composition and Temperature

-   -   Similar to KOH, the TMAH etch rate varies exponentially with        temperature. Table 4 relates silicon orientation-dependent etch        rates of TMAH to percent composition, temperature, and        orientation. Table 4 is taken directly from [2].

Etch Temper- rate ature Direction (μm Etchant (° C.) (plane) min⁻¹)Remarks Resources 5% TMAH: 60 (100) 0.33 [7] 95% H₂0 70 0.48 80 0.87 901.4 60 (110) 0.64 70 0.74 80 1.4 90 1.8 60 (111) 0.026 90 0.034 10% 60(100) 0.28 [7] TMAH: 70 0.41 90% H₂0 80 0.72 90 1.2 2% TMAH: 80 (100)0.65 [8] 98% H₂0 (111) 0.41 5% TMAH: 80 (100) 0.63 [8] 95% H₂0 (111)0.013 10% 80 (100) 0.57 [8] TMAH: (111) 0.014 90% H₂0 22% TMAH 90 (100)0.9 (110) is [9] in H₂0 (110) 1.8 fastest (111) 0.018 without surfactant22% TMAH 90 (100) 0.6 (100) is [9] in H₂0 + (110) 0.12 fastest with 0.5%(111) 0.01 surfactant surfactant 22% TMAH 90 (100) 0.6 Surfactants [9]in H₂0 + 1% (110) 0.1 effect surfactant (111) 0.009 saturates

E EDP

Similar to KOH, EDP is often used for fast removal and siliconmicromachining. Table 5 relates silicon orientation-dependent etch ratesin EDP solutions to Temperature and Orientation.

Etch rate Temperature Direction (μm Etchant (° C.) (plane) min⁻¹)Remarks References 500 ml 110 (100) 0.47 EDP ‘T’ etch [10] NH₂(CH₂)₂NH₂:(110) 0.28 Oldest EDP 88 g C₆H₄(OH)₂: (111) 0.028 formula 234 ml H₂0 ERrises to >0.83 μm/min after exposure to oxygen 500 ml 115 (100) 0.45 EDP‘F’ etch [11] NH₂(CH₂)₂NH₂: Fast etch rate 160 g C₆H₄(OH)₂: Must be usedat 160 ml H₂0 high T to avoid residue F etch above 115 (100) Faster w/[11] w/1.0 g C₆H₄N₂ pyrazine Less sensitive to oxygen Smoother F etchabove 115 (100) 1.35 [11] w/3.0 g C₆H₄N₂ 500 ml 50 (100) 0.075 EDP ‘S’etch [11] NH₂(CH₂)₂NH₂: 75 (100) 0.22 Slower etch rate 80 g C₆H₄(OH)₂:95 (100) 0.43 Suitable for 3.6 C₆H₄N₂: 66 ml 105 (100) 0.57 lower H₂0110 (100) 0.75 temperature use without residue 46.4 mol % 118 (100)Stops on p⁺⁺ [12] NH₂(CH₂)₂NH₂: 4 mol (110) % C₆H₄(OH)₂: (111) 49.4 mol% H₂0 250 ml 110 (100) [13] NH₂(CH₂)₂NH₂: (111) 45 g C₆H₄(OH)₂: 120 mlH₂0

F ISOTROPIC SILICON ETCHES

Often, isotropic etchants having dissolution rates independent oforientation are needed. These chemical mixtures tend to uniformly removematerial, and are limited by the mass transport of chemical species tothe crystal surface. The actual surface reaction rates are so great thatvariations to atomic structure do not alter the reaction speed relativeto chemical transport.

Table 6 lists several common recipes and is taken directly from [14].

Formula Comments Reference HF, HNO₃ See [14] p73 HF, HNO₃, H₂0 orCH₃COOH Various combinations [15] give different etch rates 900 ml HNO₃,95 ml HF, 15 μm/min [16] 5 ml CH₃COOH, 14 g NaClO₂ 745 ml HNO₃, 105 mlHF, 170 A/sec [17] 75 ml CH₃COOH, 75 ml HClO₄ 50 ml HF, 50 ml CH₃COOH,Epi Etching 0.2 μm/min [18] 200 mg KMnO₄ (fresh) 108 ml HF, 350 g NH₄Fper L H₂0 Epi Etching [19] n type 0.2-0.6 ohm-cm; 0.43 A/min p type 0.4ohm-cm; 0.45 A/min p type 15 ohm-cm; 0.23 A/min

G SILICON DEFECT DELINEATION ETCHES

Certain chemical etchants are strongly dependent on defects, and defectstructures in the single crystal silicon. These etchants are commonlyused to high-light or delineate defects in the material.

Table 7 lists the most common defect delineation mixtures, and is takendirectly from [14]

Shelf Formula Name Application Life Ref  1 1 ml HF, 1 ml C₂O₃ (5M) Sirtl111 Silicon 5 min [20] Approx 5 min etch  2 1 ml HF, 3 ml HNO₃, Dash 111oe 100 n or p 8 h [21] 1 ml CH₃COOH (works best on p) Approx 15 hr etch 3 2 ml HF, 1 ml K2Cr₂O₇ Secco 100 or 111 silicon 5 min [21] (0.15M) 2ml HF, 1 ml Cr₂O₃ Secco 100 or 111 silicon 5 min [21][20] (0.15M)  4 200ml HF, 1 HNO₃ P-N delineation [20]  5 60 ml HF, 30 ml HNO₃ Jenkinsgeneral use 6 wks [21][20] 60 ml H₂0 Wright does not roughen [22] 60 mlCH₃COOH, 30 ml defect free (1 g CrO₃ to 2 ml H₂0) regions Approx 30 minetch  6 2 ml HF, 1 ml HNO₃, 2 ml Silver epitaxial layer [20] AgNO₃(0.65M in faults H20)  7 5 gm H₅IO₆, 5 mg Kl in Sponheimer Etch 5-20seconds [22] 50 ml H₂O, 2 ml HF Mills junction delineation  8 Shipley112° [23]  9 6 ml HF, 19 ml HNO [23] 10 (150 g/l (1.5M) CrO₃ to Yang[24] H₂0) to HF 1:1 11 600 ml HF, 300 ml Copper [25] HNO₃ 28 g Cu(NO₃)₂,3 ml Etch H₂0 12 1000 ml H₂O, 1 drop [25] (1.0N) KOH 3.54 g kBr, .708 gKbrO₃ 13 55 g CuSO₄, SH20, 950 ml Copper [25] H₂0, 50 ml Hf Displacement14 1 ml HF, 3 ml HNO₃ White 15 secs. PN Junction etch with stron light15 3 ml HF, 5 ml HNO₃, CP-4 10 sec-3 min [26] 3 ml CH₃COOH P-N Junctions16a 25 ml HF, 18 ml HNO₃, SD1 2-4 min reveals [26] 5 ml CH₃COOH/.1Br2edge and mixed 10 ml H₂0, 1 g Cu(NO₃)₂ dislocations 16b 100 ml HF; .1 to.5 ml P stain [26] HNO3 16c 50 ml dilute Cu(NO₃)₂ N stain [26] 1 to 2drops HF 16d 4% NaOH add 40 NaClO 80° C. specimen [26] until no H₂evolution thinning (float from Si specimen on surface of etch) 17 300 mlHNO₃, 600 ml Sailer Etch 4 hr Epi [27] HF 2 ml Br₂, 24 g Stacking FaultsCu(NO₃)₂ dilute 10:1 wtih H₂O 18 a) 1) 75 g CrO₃ in 1000 ml SchimmelResistivity greater H₂0 mix 1 part 1) to 2 than .2 ohm-cm parts 48% HF(111) oe (100) approx 5 min b) mix part 1) to 2 parts Resistivity less48% HF to 1.5 parts H₂O than .2 ohm-cm 19 5 g H₅IO₆, 50 ml H₂O, PeriodicJunction 2 ml HF, 5 mg Kl HF Deliniation

H CONCLUSION

There are many wet-chemical etch recipes known for etching silicon.These processes are used for a variety of applications includingmicromachining, cleaning, and defect delineation. The detailed behaviourand rate of the etchant will vary between laboratory environments andexact processes. However, the data and phenomena recorded above havebeen reported by many researchers and manufactures.

For further details the reader is encourage to fully explore the directand indirect references sited.

I REFERENCES

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1. A package having a cavity for high frequency electrical circuitscapable of generating resonant wave modes in a range of orientationswithin the cavity, the cavity formed within a first material forcontainment of the electrical circuit, wherein the package additionallycomprises a second material forming an elongate member of graduallydecreasing cross-section towards an apex thereof which member extendsinto the cavity and comprises a plurality of discrete conductive regionsthat are configured to uniformly absorb all resonant wave modes acrossthe range of orientations.
 2. The package of claim 1 wherein the secondmaterial forms at least one elongated member having a polygonalcross-section.
 3. The package of claim 1 wherein the second materialforms at least one elongated member having a circular cross-section. 4.The package of claim 3, wherein the at least one elongated member is ofgradually decreasing cross-section towards the apex thereof.
 5. Thepackage of claim 4 wherein the at least one elongated member is conicalin shape.
 6. The package of claim 3, wherein said at least one elongatedmember comprises a plurality of elongated members in an ordered array.7. The package of claim 3, wherein said at least one elongated membercomprises a plurality of elongated members in an unordered array.
 8. Thepackage of claim 6 wherein in use the plurality of discrete conductiveregions are at oblique angles to any active circuits contained withinthe package.
 9. The package of claim 6 wherein in use the plurality ofdiscrete conductive regions are perpendicular to any active circuitscontained within the package.
 10. The package of claim 1 wherein thesecond material comprises a material selected from the group consistingof glass, plastic, ceramic, cardboard, metal and metalloid.
 11. Thepackage of claim 10 wherein the second material is selected from thegroup consisting of alumina, aluminium, brass, boron, germanium, quartz,silicon and silicon dioxide.
 12. The package of claim 10 or 11 whereinthe first and second materials are the same.
 13. The package of claim 10wherein the second material is formed by wet etching of silicon dioxide.14. The package of claim 10 wherein the second material is formed bymoulding.
 15. The package of claim 14 wherein the second material isformed by injection moulding.
 16. The package of claim 1 wherein thesecond material forms an irregular surface.
 17. The package of claim 16wherein the discrete conductive regions are electroplated.
 18. Thepackage of claim 2 wherein said at least one elongated member comprisesa plurality of elongated members in an ordered array.
 19. The package ofclaim 2 wherein said at least one elongated member comprises a pluralityof elongated members in an unordered array.